It is a general design goal for computer system component designers to reduce the complexity of memory controllers while increasing memory throughput. Computer systems may become memory-access-limited if the typical CPU cycle time is greater than an order of magnitude faster than the cycle time of the main memory components such as DRAMs. Recent attempts by DRAM manufacturers to reduce memory access time and component latency include the implementation of page mode and nibble mode features (as described infra) to these devices. These features have proven useful for decreasing necessary access time when the data being sought are in locations proximate to each other, i.e,, when the addresses for consecutive data accesses are found relatively close to one another in physical memory.
DRAM's are typically addressed by a bit pattern of a predetermined length which is dependent upon DRAM size. For example, a one megabit DRAM would require a minimum of 20 bits to address every memory location (2.sup.2 =1,048,576). Of these 20 bits, typically 10 are for the row address and the remaining 10 are for the column address of the memory location of the DRAM. In operation, however, memory addresses frequently comprise more than these 20 minimum bits to address the DRAM array locations. For example, additional bits may be required for choosing the particular DRAMs to be accessed.
In operation, a conventional DRAM has the portion of the DRAM address dedicated to row identification (for example, 10 bits of the 20 bits described above) input to a row address decoder, usually upon receipt of a row access strobe (RAS) signal on the appropriate signal line. The portion of the DRAM address dedicated to column identification is input to a column address decoder, usually upon receipt of a column address strobe (CAS) signal on another input line.
Generally, memory access to a DRAM unit can be viewed as comprising up to seven stages, with each stage requiring a specific time period. Specifically, there is the RAM select stage during which the particular memory unit to be accessed is chosen; a row address set-up stage which corresponds to the length of time that a specific row address must be stable prior to the RAS strobe; the RAS stage to strobe the row address to a row address decoder; the column address set-up stage which corresponds to the length of time that a specific column address must be stable prior to the CAS strobe; the CAS stage to strobe the column address to a column address decoder; the data slot stage, during which data located in the addressed location is retrieved or deposited; and an address release stage which frees the system for receipt of the next address.
In DRAM implementation the column address set-up stage requires a significant amount of time compared to the other six stages. For example, in a typical memory access to a DRAM using the seven stages just discussed, 85-100 nanoseconds may be needed to complete the middle five stages of the access. Of this total time, the column address set-up alone may take 30 nanoseconds. Eliminating, or at least reducing the column address set-up time would improve memory access time.
The nibble mode may be generally defined as operating with a common row address and an incremental column address. The operation of a DRAM in this manner is useful for memory accesses when the data sought is at consecutive addresses in memory. This mode allows for a new memory address to be provided to the DRAM on the initial RAS and CAS cycles. A DRAM operating in the nibble mode contains an internal incremental counter which increments the column address by one for each CAS cycle with wrap around, for example, a 2 bit counter would allow four consecutive address accesses. Such an arrangement eliminates the column address set-up time for all but the initial CAS cycle, and therefore memory access time is significantly reduced.
A DRAM having nibble mode capability is especially useful for reading program instructions from memory since such instructions tend to reside in consecutive memory locations. In the case of cache memory devices, nibble mode-capable DRAMs are useful for cache fills during read operations which often require fill sizes greater than one word, with such fill locations typically occurring consecutively. Nibble mode DRAMs are beneficial for read operations because of the tendency for reads to retrieve blocks of data as opposed to write operations which typically deposit data in non-consecutive locations in memory.
In turn, page made may be generally defined as operating with a common row address and a varying column address. A DRAM having page mode capability is useful for memory accesses which have the same row addresses but different column addresses. The operation of a page mode DRAM provides for the input of a single row address and unique column addresses for each CAS cycle until the RAS signal changes state. Page mode operations require more time than nibble mode operations since there is a column set-up time at each cycle. However, page mode operations are more useful over a wider data set than nibble mode operations, since it can be used for all data on the same page without being limited to consecutive data elements.
Heretofore it was necessary to choose between nibble mode and page mode operations in an attempt to optimize a particular memory subsystem for reads or writes. This, however, helped only if you made the right choice for the particular type of operations most likely to be run on the system. If the wrong choice was made, the user saw no memory access time advantage, and in fact the memory access time could have become worse.
In their attempts to come up with DRAM designs to reduce memory access time, manufacturers have been frustrated by the inability to modify standard DRAM inputs and signal connections (so called "DRAM footprints"). That is, any gains in DRAM memory access time came at the expense of more complicated, pin designs or hardware and software of greater complexity.